Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
Document Type
Conference Proceeding
Publication Date
2016
Abstract
This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware implementation in commercial FPGA boards, and experimentally assess its performance.
Recommended Citation
Corvera, Jan Alain; Dumlao, Samuel Matthew G.; Reyes, Rosula SJ; Castoldi, Piero; Andriolli, Nicola; and Cerutti, Isabella, (2016). Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks. Archīum.ATENEO.
https://archium.ateneo.edu/ecce-faculty-pubs/56