Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks

Authors

Jan Alain Corvera
Samuel Matthew G. Dumlao, Ateneo de Manila University
Rosula SJ Reyes, Ateneo de Manila UniversityFollow
Piero Castoldi
Nicola Andriolli
Isabella Cerutti

Document Type

Conference Proceeding

Publication Date

2016

Abstract

This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware imple­mentation in commercial FPGA boards, and experimentally assess its performance.

Recommended Citation

J. A. Corvera, S. M. G. Dumlao, R. Reyes, P. Castoldi, N. Andriolli, and I. Cerutti, "Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks," in Advanced Photonics 2016 (IPR, NOMA, Sensors, Networks, SPPCom, SOF), OSA Technical Digest (online) (Optical Society of America, 2016), paper NeM3B.4.