Title

Design of an Interface Test Adapter for Sequential Testing of Transient Voltage Suppressor Diodes to Reduce Test Cycle Time

Date of Award

2021

Document Type

Thesis

Degree Name

Master of Science in Electronics Engineering

Department

Electronics, Computer, and Communications Engineering

First Advisor

Patricia Angela R. Abu, PhD; Carlos M. Oppus, MS; Rosula S.J. Reyes, PhD

Abstract

The advancement in semiconductor circuit design, particularly its miniaturization has increased the circuit sensitivity to electrical stresses. To protect the circuits, transient voltage suppressor (TVS) diodes are used. This device must be tested with the use of a high-power tester that is capable of surge high inrush power. In a test manufacturing company that employs manual testing of TVS diodes, the cycle time (CT) increases which results in a decrease in the number of units per hour (UPH). The UPH can be increased if the cycle time of the process and human intervention is reduced. In this study, the Design for Six Sigma (DFSS) is used for the design methodology to develop an interface test adapter (ITA) to increase the UPH tested. The DFSS is composed of five phases known as DMADV (Define, Measure, Analyze, Design, and Verify), it is a process flow that guides the research in the creation of ITA. The first phase defines the problems, objectives, and design consideration of the research, the second phase measures the performance of the current setup by determining the CT of each step involved in the current process, the third phase analyzes the obtain data for possible problem solution by determining which steps in the process can be improved, fourth phase design and fabricate the chosen ITA with the best performance that meets the design requirement from the three evaluated concepts, and the fifth phase verify the actual performance of the ITA. The ITA is interfaced between the current test machine and the unit under test (UUT). It consists of a fixture, which holds the UUT, and an FPGA board, which manages the process. It is electrically isolated from the tester and UUT to avoid v interference with the reading. The ITA automates the current fixture in testing the eight bidirectional TVS diodes devices in a single unit of vertical array package to reduce the test cycle time. It also minimizes human intervention that avoids human handling error and inconsistency in the process cycle time. Results show that the cycle time per unit has decreased by 20.57%. In terms of UPH tested, this is equivalent to a 48.80% improvement.

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