Hardware Comparison of Schedulers for Modular Optical Interconnection Networks

J C. Borromeo
Isabella Cerutti
Piero Castoldi
Rosula SJ Reyes, Ateneo de Manila University
Nicola Andriolli


We present the first FPGA implementation of the Two-Step Scheduler framework for modular optical interconnection networks. The longest-queue-first scheduling algorithm guarantees the lowest latency, while the iSLIP algorithm minimizes the hardware resources and scheduling duration.